1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as a flash memory and more particularly, it relates to a constitution of a reference cell which is a reference at the time of readout, or at the time of verification for program or erase of a memory cell of the nonvolatile semiconductor memory device.
2. Description of the Related Art
Various kinds of methods are employed in order to read a storage state of a memory cell in a semiconductor memory device. A description will be made of a flash memory which is one of the nonvolatile semiconductor memory devices as one example. The flash memory is constituted such that each memory cell comprises a memory transistor having a floating gate structure and information is stored according to an amount of charges (electrons) input to the floating gate of each memory cell. More specifically, when many electrons are stored in the floating gate, an inversion layer is not likely to be formed in a channel region, so that the threshold voltage of the memory cell becomes high (which is defined as a programmed state). Meanwhile, when the electrons are discharged from the floating gate, the inversion layer is likely to be formed in the channel region and the threshold voltage of the memory cell becomes low (which is defined as an erased state). In order to determine whether the state of the selected memory cell is the programmed state or the erased state at high speed, a reference memory cell having a middle threshold voltage between the programmed state and the erased state is input to a differential input type of sense amplifier.
In addition, in a case of a flash memory in which multi-level data (4-value data, for example) can be stored in each memory cell, there are four storage states shown in FIG. 4 depending on the amount of charges stored in the floating gate.
The state in which the charge quantity is smallest is “11”, which corresponds to the erased state. In order to transit from “11” state to any one of storage states “10”, “01”, and “00”, the charges are injected to the floating gate of the memory cell, which operation is called a program operation.
The program operation can be performed only in the direction in which the charges of the floating gate are increased. For example, in order to transit from the state “01” to the state “10”, it is necessary to perform the erase operation once to implement the state “11” and then to perform the program operation to implement the state “10”. Here, although the program operation can be performed by a memory cell, the erase operation is performed by the plural memory cells.
The general program operation of the flash memory will be described with reference to FIG. 1. When the program operation is performed on the flash memory, a program command is input through an I/O pad 22 and an address of the memory cell for the program operation is input through an address pad 1 to be specified in a first cycle. The inputted command is decoded by a command decoder 23 and when it is the program command, command decoder 23 directs a control circuit 13 to controls data (program data) inputted from the I/O pad 22 so as to be programmed in the address inputted from the address pad 1 in a second cycle.
The address of the memory cell for the program operation is decoded in a main row decoder 4 and a main column decoder 8 through an address multiplexer 3 and at the same time, the plural number (eight, for example) of flash cells are selected.
In order to raise the threshold voltage of the flash cell, channel hot electrons which are generated when the source of the memory cell transistor is set at 0 V and a high voltage is applied to its gate and drain are injected into the floating gate.
A pulse pattern generated in a program circuit 12 based on the program data determines whether the data is programmed in the selected memory cell or which storage state is implemented.
The voltage which is divided from the high voltage, for example 12 V raised by a pumping circuit 14 depending on the storage state (threshold voltage) for the programming is outputted from a digital/analog converter circuit (D2A) 16 and is applied to the gate of the memory cell through the main row decoder 4. The control signal from the control circuit 13 determines the voltage value to be outputted from the D2A 16.
A voltage, 5 V, for example is applied only to the drain of the memory cell for the program in the selected memory cell through the program circuit 12 and the main column decoder 8 for a certain period of time (program pulse). A voltage 0 V is applied to the drains of the cells which are not for the program so that the charges are not injected thereto to prevent the threshold voltage from being changed (that is, programmed).
After the program pulse is applied, it is verified whether the desired threshold voltage is attained by comparing it with the threshold voltage of the reference memory cell of a reference array 11 selected by a reference column decoder 7 and a reference row decoder 5, by the sense amplifier 9. Although the verifying operation is a kind of the readout operation, it is performed in order to secure the operation margin at the time of reading. Therefore, the operation margin is provided by setting the threshold voltage of the reference cell to be used at the time of the verification so as to be different from the threshold voltage of the reference cell to be used at the time of the reading when a wafer is tested.
The verifying operation will be described with reference to FIG. 1. Since the selection of the memory cell is the same as at the time of the programming, its description will be omitted. The verifying operation is performed by setting the source, the drain, and the gate of the memory cell at 0 V, at a low voltage (1 V, for example), at a readout voltage (6 V, for example), respectively. This voltage setting is in common with the memory cell of a main memory array 10 and the reference memory cell of the reference array 11, and the voltage which is raised by the pumping circuit 14 and divided by the D2A 16 is applied to the main memory array 10 through a main high-voltage switch circuit 17 and to the reference array 11 through a reference high-voltage switch circuit 18.
When the threshold voltage of the memory cell after the program operation is lower than the threshold voltage of the reference memory cell, a signal level “1” (showing that the programming is not completed yet), for example is sent from the sense amplifier 9 to the program circuit 12 and then the program pulse is applied again. After the pulse is applied, the verifying operation is performed again, so that the program pulse is applied until the sense amplifier 9 outputs the signal level “0” (showing that the programming is completed).
A description will be made of how a readout margin is provided by the verifying operation with reference to FIG. 4. When the data “01” is to be programmed, for example, the reference memory cell having the threshold voltage PV2 is used in the verifying operation. As described above, since the programming is performed until the threshold voltage of the memory cell exceeds the threshold voltage of the reference memory cell, the threshold voltage of the memory cell after the programming is completed is surely more than the threshold voltage PV2.
Since the data “01” is read using the reference memory cell having a threshold voltage M shown in FIG. 4, there is a threshold voltage difference of at least (PV2−M) between the memory cell for the readout and the reference memory cell (threshold voltage M). In general, as the threshold voltage difference between the two memory cells to be input to the sense amplifier is larger, the data can be read more stably at higher speed. That is, as the threshold voltage difference (PV2−M) is larger, the readout margin is increased.
Therefore, conventionally, the threshold voltage for the ordinal readout is distinguished from the threshold voltage for the verifying operation in order to provide enough readout margin, and there are prepared the plural reference memory cells which are individually set by the program state so as to correspond to the multiple-level memory (refer to JP-A 59-104796 and JP-A 2002-100192, for example).
Although the threshold voltage of each reference memory cell is set using a tester at the time of a test, when the threshold voltage setting of the reference memory cell (Cell A) for the readout and the reference memory cell (Cell B) for the verification are shifted by the error of the tester as shown in FIG. 8, it is considered that the provided threshold voltage difference could be smaller than the set threshold voltage difference. More specifically, when the threshold voltage of the reference memory cell for the verification is shifted in the negative direction and the threshold voltage of the reference memory cell for the readout is shifted in the positive direction, the threshold voltage difference becomes smaller than the set value. If such shifts occur, there is a problem such that the operation margin at the time of the readout becomes small.
Since the nonvolatile semiconductor memory device meets demands for high capacity, the memory cell tends to become a multi-level cell and it is necessary to provide the reference memory cells having the many kinds of threshold voltages in order to determine many storage levels. That is, the number of the reference memory cells and level sense circuits incidental to them are increased.
In addition, the following problems are generated when the threshold voltage of the reference memory cell is set (referred to as “trimming”) at the time of the test in the conventional nonvolatile semiconductor memory device. That is, since the number of the reference memory cells of the nonvolatile semiconductor memory device is increased because of an increase in capacity, multi-level memory and the like, the number of the reference memory cells to be trimmed is increased. In addition, although high precision of the trimming of the reference memory cell is required because of the multi-level cells, as the number of the reference cells is increased and as the trimming step becomes finer to provide higher precision, the trimming time is more increased; this causes production efficiency to be lowered.